Field effect transistor structure with partially isolated source/drain junctions and methods of making same

ABSTRACT

A microelectronic structure includes at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type. In a further aspect of the invention, a process for forming a microelectronic structure, such as a MOSFET, having at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type includes forming a recess having a surface, forming a dielectric material over a portion of the surface of the recess, and back-filling the recess to from a source/drain terminal.

REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to U.S. application Ser. No.09/474,836, filed Dec. 30, 1999.

FIELD OF THE INVENTION

[0002] The trend of integrating more functions on a single substratewhile operating at ever higher frequencies has existed in thesemiconductor industry for many years. These higher operatingfrequencies are generally made possible by advances in bothsemiconductor manufacturing and digital systems design and architecture.

[0003] Improvements in semiconductor manufacturing technology that leadto improved operating frequencies are generally related to improvementsin the electrical characteristics of circuit elements, such astransistors and capacitors, and the structures used to interconnect thevarious circuit elements.

[0004] More particularly, one way to realize gains in the operatingfrequency characteristics of integrated circuits includes reducingparasitic capacitance. Parasitic capacitance tends to slow down theoperation of integrated circuits because more current is required tocharge and discharge the parasitic capacitors and therefore more time isrequired to drive various circuit nodes to the desired voltage. Asignificant amount of parasitic capacitance in integrated circuitsexists in the junction capacitance associated with field effecttransistors typically found on an integrated circuit.

[0005] What is needed is a field effect transistor structure havingsource/drain terminals with reduced junction capacitance. What isfurther needed is a method of manufacturing such a structure.

SUMMARY OF THE INVENTION

[0006] Briefly, a microelectronic structure includes at least onesource/drain terminal of a first conductivity type that is partiallyisolated from a region of semiconductor material of a secondconductivity type.

[0007] In a further aspect of the invention, a process for forming amicroelectronic structure having at least one source/drain terminal of afirst conductivity type that is partially isolated from a region ofsemiconductor material of a second conductivity type includes forming arecess having a surface, forming a dielectric material over a portion ofthe surface of the recess, and back-filling the recess to form asource/drain terminal.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 is a schematic cross-section of a conventional MOSFET.

[0009]FIG. 2 is a schematic cross-section showing the structure of apartially completed MOSFET with recesses formed adjacent to the sidewallspacers and nitrogen implanted into the bottom portion of the recesses.

[0010]FIG. 3 is a schematic cross-section showing the structure of FIG.2, after a selective silicon epi formation operation fills the recessesand the implanted nitrogen has been annealed.

[0011]FIG. 4 is a schematic cross-section showing the structure of apartially completed MOSFET with recesses formed adjacent to the sidewallspacers and silicon nitride formed over the bottom and side surfaces ofthe recesses.

[0012]FIG. 5 is a schematic cross-section showing the structure of FIG.4, after an etching operation removes silicon nitride from side surfaceof the recesses.

[0013]FIG. 6 is a schematic cross-section showing the structure of FIG.3, after back-filling of the recesses.

[0014]FIG. 7 is a schematic cross-section showing the structure of FIG.6, after excess silicon nitride is removed from the MOSFET structure.

DETAILED DESCRIPTION

[0015] Overview

[0016] Conventional source/drain junction formation is accomplished byone or more ion implantation operations that are generally self-alignedto the gate electrode, or alternatively, aligned to sidewall spacersthat are adjacent to the gate electrode. In such a process, ions of afirst conductivity type (p- or n-) are implanted into a semiconductormaterial of a second conductivity type (n- or p-). A capacitance betweenthe two nodes represented by the different conductivity types arises attheir junction and is a function of the width of the depletion regionformed at the junction. The width of the depletion region may beaffected by various conditions including but not limited to, thematerials used, the concentrations of those materials, an externallysupplied voltage, if any, applied across the junction, and so on. Intypical circuit applications these capacitances are undesirable and areoften referred to as parasitic capacitances.

[0017] In order to reduce the parasitic junction capacitance, variousstructures have been used wherein the source/drain material is formed onan insulating layer, such as silicon dioxide. A disadvantage of suchstructures is that they generally tend to create a floating bodyterminal in a MOSFET because the channel region is completely isolatedfrom the well (or bulk semiconductor).

[0018] Embodiments of the present invention provide partial isolation ofthe source/drain terminal from the well (or bulk semiconductor) whileleaving the channel region, i.e., the body terminal, electricallycoupled to the well (or bulk semiconductor) rather than floating.

[0019] More particularly, source/drain terminals in accordance with thepresent invention include a dielectric layer, such as, for example,silicon nitride, disposed between a portion of the source/drain terminaland the well (or bulk semiconductor). In one illustrative embodiment ofa process in accordance with the present invention, at least one recesshaving a surface is formed in a substrate, self-aligned to a gateelectrode, nitrogen is implanted, self-aligned to the gate electrode,into a portion of the surface of the recess, an epitaxial silicon layeris then formed to back-fill the recess and a high temperature anneal isperformed. In an alternative illustrative embodiment of a process inaccordance with the present invention, at least one recess having abottom surface and a side surface is formed self-aligned to a gateelectrode; a silicon nitride layer is formed over the top and sides ofthe gate electrode and over the bottom and side surfaces of the recesswith the nitride layer being thicker and denser on the bottom surfacethan on the side surface; the nitride is removed from at least the sidesurface of the recess thereby exposing a portion of the substrate, andan semiconductor layer is formed extending laterally outward from theexposed side surface to back-fill the recess. It should be understood,that although the illustrative embodiments above are described inconnection with various operations being self-aligned to the gateelectrode, this should also be taken to include being self-aligned tosidewall spacers which are commonly used adjacent to the gate electrodeof a MOSFET.

[0020] Terminology

[0021] The terms, chip, integrated circuit, monolithic device,semiconductor device or component, microelectronic device or component,and similar terms and expressions are often used interchangeably in thisfield. The present invention is applicable to all the above as they aregenerally understood in the field.

[0022] Epitaxial layer refers to a layer of single crystal semiconductormaterial.

[0023] The term “gate” is context sensitive and can be used in two wayswhen describing integrated circuits. As used herein, gate refers to theinsulated gate terminal of a three terminal FET when used in the contextof transistor circuit configuration, and refers to a circuit forrealizing an arbitrary logical function when used in the context of alogic gate. A FET can be viewed as a four terminal device when thesemiconductor body is considered.

[0024] Polycrystalline silicon is a nonporous form of silicon oftenformed by chemical vapor deposition from a silicon source gas, or othermethods, and has a structure that contains crystallites or domains withlarge-angle grain boundaries, twin boundaries, or both. Polycrystallinesilicon is often referred to in this field as polysilicon, or sometimesmore simply as poly.

[0025] Source/drain terminals refer to the terminals of a FET, betweenwhich conduction occurs under the influence of an electric field,subsequent to the inversion of the semiconductor surface under theinfluence of an electric field resulting from a voltage applied to thegate terminal. Source/drain terminals are typically formed in asemiconductor substrate and have a conductivity type (i.e., p-type orn-type) that is the opposite of the conductivity type of the substrate.Sometimes, source/drain terminals are referred to as junctions.Generally, the source and drain terminals are fabricated such that theyare geometrically symmetrical. Source/drain terminals may includeextensions, sometimes referred to as tips, which are shallower thanother portions of the source/drain terminals. The tips typically extendtoward the channel region of a FET, from the main portion of thesource/drain terminal. With geometrically symmetrical source and drainterminals it is common to simply refer to these terminals assource/drain terminals, and this nomenclature is used herein. Designersoften designate a particular source/drain terminal to be a “source” or a“drain” on the basis of the voltage to be applied to that terminal whenthe FET is operated in a circuit.

[0026] Substrate, as used herein, refers to the physical object that isthe basic workpiece that is transformed by various process operationsinto the desired microelectronic configuration. A substrate may also bereferred to as a wafer. Wafers, may be made of semiconducting,non-semiconducting, or combinations of semiconducting andnon-semiconducting materials.

[0027] The term vertical, as used herein, means substantiallyperpendicular to the surface of a substrate.

[0028] A cross-sectional view of a conventional FET is shown in FIG. 1.A gate electrode 102 is disposed superjacent a gate dielectric layer104, which in turn is disposed superjacent a semiconductor substrate101. Sidewall spacers 106 are disposed adjacent to the stack formed bygate dielectric 104 and gate electrode 102. Source/drain terminals 108are disposed, adjacent to sidewall spacers 106, in substrate 101.Although a variety of materials may be used, it is typical to havesubstrate 101 be silicon, gate dielectric 104 be an oxide of silicon,gate electrode 102 be polysilicon, and sidewall spacers be an insulatorsuch as silicon nitride or silicon dioxide.

[0029] Still referring to FIG. 1, it will be appreciated thatsource/drain terminals 108 are normally reversed biased with respect tosubstrate 101. The reversed biased junctions act as voltage variablecapacitors since the width of the depletion region associated with areversed biased junction is a function of the voltage across thejunction. In addition to the capacitance associated with thesejunctions, there is also a leakage current that is associated with thejunctions. Reducing both the parasitic junction capacitance and reducingthe reverse-biased junction leakage current leads to higher performancecircuits.

[0030] Additionally, source/drain terminals 108 of the conventional FETof FIG. 1, are susceptible to alpha particle induced soft errors. Inoperation, charge is often stored at the capacitor which is formed bythe reversed-biased source/drain junction. Alpha particles from theenvironment frequently strike the substrate, passing through thesubstrate and generating carriers. The carriers may then migrate towardsthe charged source/drain junctions and affect the voltage at those nodesby changing the amount of stored charge. This phenomenon is sometimesreferred to “zapping”. As source/drain terminals 108 are reduced in sizeby manufacturers to increase integration density, the smallersource/drain terminals are able to store correspondingly less charge andare therefore correspondingly more susceptible to the effects ofzapping. Protecting these nodes from zapping by isolating them fromalpha particle induced carriers is desirable.

[0031] Referring to FIGS. 2-3, a first illustrative embodiment of thepresent invention is described. As shown in FIG. 2, a wafer is processedin known ways to form one or more regions of semiconductor material 201isolated by shallow trench isolation (STI) structures 210, wherein gatedielectric layer 208 is formed on the surface of semiconductor material201, gate electrodes 202 are formed superjacent gate dielectric layer208, and sidewall spacers 206 are typically formed adjacent to thesidewall of gate electrode 202. In embodiments of the present invention,sidewall spacers 206 are typically multi-layer spacers. Multi-layerspacers may have an oxide layer formed from tetraethylorthosilicate(TEOS) and an overlying nitride layer formed from bis-(tertiarybutylamino) silane (BTBAS). As further shown in FIGS. 2 and 3, a barrierlayer 204 is formed over the top surface of gate electrode 202. Barrierlayer 204 may be an anti-reflective coating sometimes referred to asBARC (bottom anti-reflective coating). Barrier layer 204 may be asilicon nitride layer, however any suitable material may be used thatsubstantially prevents the polysilicon of gate electrode 202 from beingetched during a process operation in which recesses 212 are formed insemiconductor material 201. For example, barrier layer 204 may be, butis not required to be, an oxide layer with an overlying oxynitridelayer. Barrier layer 204 may also be referred to as a poly hardmask.

[0032] Subsequent to the formation of the gate electrode and STIstructures described above, the surface of semiconductor material 201 isetched, self-aligned to the gate electrode and sidewall spacers so as toform trenches, or recesses 212. In the illustrative embodiment,substrate 201 is a silicon wafer, gate dielectric layer 208 is a silicondioxide layer, and gate electrode 202 is formed from polysilicon.Although gate dielectric layer 208 is typically a thin layer of oxidizedsilicon, the thickness and chemical make-up of this gate insulator layermay be varied within the scope of the invention.

[0033] Recesses 212 are formed in the wafer at locations where thesource/drain terminals of the FET will be located. The recesses areformed by the anisotropic etch of the wafer. The etch chemistry andconditions are preferably chosen such that the etch is highly selectiveand preferentially etches the wafer rather than the side wall spacers orthe gate dielectric layer. In the illustrative embodiment, wherein thewafer is silicon, the gate dielectric is an oxide of silicon, the gateelectrode is polysilicon and the side wall spacers are silicon nitride,an plasma etch conditions such as a pressure of 400 to 550 mT, a powerof 250 to 350 Watts, a plate spacing of 0.5 to 1 cm, a He flow rate of50 to 150 sccm , and Cl₂ flow rate of 100 to 200 sccm.

[0034] After the recesses are formed a cleaning operation is performedon the recess surfaces. A recess surface clean in accordance with thepresent invention may include a plasma etch in a parallel plate typeplasma etcher such as those available from LAM Research Corp. Plasmaconditions for the recess surface clean may include a pressure in therange of 200 to 300 mT, power in the range of 25 to 100 W, a platespacing in the range of 0.8 to 1.5 cm, a He flow rate in the range of200 to 350 sccm, and an SF6 flow rate in the range of 25 to 100 sccm. Inone embodiment, the pressure is approximately 250 mT, the power isapproximately 50 W, the plate spacing is approximately 1.1 cm, the Heflow rate is approximately 150 sccm, and the SF₆ flow rate isapproximately 50 sccm.

[0035] Those skilled in the art and having the benefit of thisdisclosure will recognize that the operations and structures shown anddescribed herein, are compatible with various field oxide isolationarchitectures. Examples of field oxide isolation architectures includeshallow trench isolation regions in a surface of a substrate, and theolder local oxidation of silicon (LOCOS), which typically formednon-planarized oxide isolation regions.

[0036] Still referring to FIG. 2, an N₂ implant operation is performedinto recesses 212, self-aligned to the gate electrode and the sidewallspacers. The N₂ implant operation is typically carried out with a doseranging from 5×10¹⁵ to 1×10¹⁷ atoms/cm², and an energy ranging from 10KeV to 20 KeV. That is, gate electrode 204 and sidewall spacers 206 actas barriers to the ion implantation operation. Subsequent to the implantoperation, the wafer is cleaned with an ex situ HF dip. Alternatively,this cleaning operation may be achieved by an SF₆ dry etch.

[0037] Alternatively, carbon may be implanted rather than nitrogen. Insuch an alternative process, a silicon carbide layer is formed as adielectric to isolate a portion of the source/drain terminal.

[0038] Referring to FIG. 3, recesses 212 are back-filled using aselective Si deposition process. That is, the recesses are filled withsilicon that is substantially single crystal, and takes its crystalorientation from that of the semiconductor material 201 which is foundat the surface of recesses 212. In one embodiment of the presentinvention, the selective Si deposition takes place in a reactionchamber, such as an ASM Epsilon 2000 single wafer GVD reactor, at atemperature between 700° C. and 900° C., with an H₂ carrier gas with aflow rate between 10 and 40 slm, a dichlorosilane (SiH₂Cl₂) flow ratebetween 25 and 200 sccm, an HCl flow rate between 10 and 200 sccm, apressure between 5 Torr and 200 Torr, and a susceptor rotation ofapproximately 35 rpm. In one embodiment, the deposition temperature isapproximately 800° C., the H₂ carrier gas with a flow rate isapproximately 20 slm, the SiH₂Cl₂ flow rate is approximately 120 sccm,the HCl flow rate is approximately 45 sccm, the pressure isapproximately 20 Torr, and a deposition rate is achieved wherein a 1000angstrom film can be deposited in approximately 6 minutes.

[0039] Subsequent to the selective Si deposition process, layer 204 isremoved, typically by a wet etch. Subsequently, a high temperatureanneal is performed, resulting in, among other things, the formation ofa silicon nitride layer 215 below the source/drain terminals. Of course,if carbon rather than nitrogen was implanted, region 215 would be asilicon carbide layer. Various other known operations may then beperformed in order to form the various levels of interconnection andinsulation typically found on integrated circuits.

[0040] An alternative embodiment of the present invention is describedin conjunction with FIGS. 4-7. This embodiment differs from thatdescribed in connection with FIGS. 2-3, in that rather than implantingand annealing nitrogen to form a silicon nitride layer, a depositionoperation is performed to provide a silicon nitride layer to partiallyisolate source/drain terminals from the substrate in which they areformed. More particularly, FIG. 4 shows a wafer which has been processedin known ways to form one or more regions of semiconductor material 201isolated by shallow trench isolation structures 210, wherein gatedielectric layer 208 is formed on the surface of semiconductor material201, gate electrodes 202 are formed superjacent gate dielectric layer208, and sidewall spacers 206 are typically formed adjacent to thevertical sidewalls of gate electrode 202. As further shown in FIG. 4, abarrier layer 204 is formed over the top surface of gate electrode 202.Barrier layer 204 may be an anti-reflective coating such siliconnitride, however any suitable material may be used that substantiallyprevents the polysilicon of gate electrode 202 from being etched duringa process operation in which recesses 212 are formed in semiconductormaterial 201. Subsequent to the formation of the gate electrode and STIstructures described above, the surface of semiconductor material 201 isetched, self-aligned to the gate electrode and sidewall spacers so as toform trenches 212. In the illustrative embodiment, substrate 201 is asilicon wafer, gate dielectric layer 208 is a silicon dioxide layer, andgate electrode 202 is formed from polysilicon.

[0041] Still referring to FIG. 4, approximately 30-50 nm of siliconnitride is directionally deposited over the surface of the wafer,including the surface of recess 212, the top and side surfaces ofsidewall spacers 206, and the top surface of barrier layer 204 usingplasma enhanced chemical vapor deposition (PECVD). This depositionoperation results in a silicon nitride layer 402 along the bottomportion of recess 212 and a silicon nitride layer 403 along the sideportion of recess 212 and the side surface of sidewall spacers 206, asshown in FIG. 4. Silicon nitride layer 402 is thicker and denser thansilicon nitride layer 403. In an exemplary process in accordance withthe present invention, a morphologically non-conformal nitride layer isdeposited in a parallel plate direct plasma reactor, such as, forexample, an Applied Materials Precision 5000. A wafer is placed on agrounded ceramic susceptor (i.e., the lower plate) and RF power (13.54MHz) is delivered to an upper gas distribution plate. The plate spacingis in the range of 6 to 15 mm, the pressure is in the range of 500 to1500 mtorr, the temperature is in the range of 250° C. to 350° C., theRF power is in the range of 0.02 to 0.5 W/cm², the SiH₄ flow rate is inthe range of 0.01 to 0.05 sccm, the NH₃ flow rate is in the range of 0.1to 0.3 sccm, and the N₂ flow rate is in the range of 2 to 6 sccm. In oneembodiment, the plate spacing is approximately 12 mm, the pressure isapproximately 700 mTorr, the temperature is approximately 275° C., theRF power is approximately 0.16 W/cm2, the SiH₄ flow rate isapproximately 0.02 sccm, the NH₃ flow rate is approximately 0.2 sccm,and the N₂ flow rate is approximately 3 sccm. A nominal nitride layerthickness of 500 angstroms is used in one embodiment of the presentinvention.

[0042] Referring to FIG. 5, it can be seen silicon nitride 403 has beenremoved from the side portion of recesses 212 and the side of sidewallspacer 206, while silicon nitride 402 remains along the bottom surfaceof recess 212. Silicon nitride 403 is typically removed by etching intrimix for approximately 2 minutes. This permits the removal of nitride403 while still leaving between approximately 20 nm to 30 nm of nitride402 on the bottom portion of recess 212. Following the dip in trimix,the wafer is cleaned with a short SF₆ dry etch so as to prepare the sideportion of recess 212 for selective silicon deposition. The side portionof recesses 212 act as a nucleation site for a subsequent operation inwhich recesses 212 is back-filled.

[0043] Referring to FIG. 6, recesses 212 are back-filled with aselective silicon deposition layer 408 that is grown laterally outwardfrom the side portion of recess 212. This lateral formation producessource/drain regions 408 that are partially isolated from the substrateby silicon nitride layer 402. Typically, source/drain regions 408 areformed of undoped silicon. Those skilled in the art and having thebenefit of this disclosure will appreciate that alternative embodimentsof the present invention may include the formation of source/drainregions 408 that may be either p-type or n-type depending on the gasmixtures used during the selective silicon deposition.

[0044]FIG. 7 shows the structure of FIG. 6, after the remaining portionsof silicon nitride 403 overlying the top surface of sidewall spacers206, and silicon nitride 402 overlying the top surface of barrier layer204 have been removed by etching. As is further shown in FIG. 7, barrierlayer 204 is also removed from the top surface of gate electrode 202. Atthis point the structure of FIG. 7, may be subjected to conventionalprocessing steps such as, for example, the formation silicides on theexposed surfaces of the source/drains and gate electrode.

[0045] Those skilled in the art and having the benefit of thisdisclosure will recognize that the operations and structures disclosedabove are applicable to the formation of both n-channel FETs (NFETs) andp-channel FETs (PFETs). NFETs and PFETs are structurally similar,however the relative placement of p-type and n-type dopants isdifferent. That is, a PFET includes p-type source/drain terminals in ann-type body, and an NFET includes n-type source/drain terminals in ap-type body.

[0046] Conclusion

[0047] Embodiments of the present invention provide microelectronicstructures such as, for example, FETs with source/drain terminalspartially isolated from the well (or bulk semiconductor) in which theyare formed. Further embodiments of the present invention provide methodsof manufacturing such structures.

[0048] FETs embodying the present invention include back-filledsource/drain terminals. In one embodiment, the doping concentration ofthe source/drain terminals can be controlled by controlling the gasmixture, temperature, and pressure, in a reaction chamber. Formation ofthe source/drain terminals in this way also provides increased marginfor the thermal budget of the manufacturing process, since a hightemperature operation is not required to activate the dopants, or tothermally in-diffuse the dopants into the tip portion of thesource/drain terminals.

[0049] An advantage of particular embodiments of the present inventionis that parasitic junction capacitance is reduced.

[0050] An further advantage of particular embodiments of the presentinvention is that charge leakage pathways between a source/drainterminal and the substrate are reduced.

[0051] A still further advantage of particular embodiments of thepresent invention is that source/drain terminals are provided with ameasure of shielding from carriers generated by events such as alphaparticle strikes.

[0052] It will be understood by those skilled in the art having thebenefit of this disclosure that many design choices are possible withinthe scope of the present invention. For example, structural parameters,including but not limited to, gate insulator thickness, gate insulatormaterials, gate electrode thickness, sidewall spacer material,inter-layer dielectric material, isolation trench depth, and S/D andwell doping concentrations may all be varied from that shown ordescribed in connection with the illustrative embodiments. Thedielectric layer formed at the bottom portion of the recesses may besilicon carbide rather than silicon nitride. Also, the operation offorming recesses and back filling with material may be repeated totailor the shape and doping profile of the source/drain terminals.

[0053] It will be understood that various other changes in the details,materials, and arrangements of the parts and steps which have beendescribed and illustrated may be made by those skilled in the art havingthe benefit of this disclosure without departing from the principles andscope of the invention as expressed in the subjoined Claims.

What is claimed is:
 1. A method of forming a source/drain terminal,comprising: masking a portion of a semiconductor surface; forming arecess in the semiconductor surface, adjacent to the masked portion, therecess having a bottom portion and a side portion; implanting ions intothe bottom portion; and selectively forming an undoped silicon layerdisposed at least partially within the recess.
 2. The method of claim 1,wherein masking a portion of the semiconductor surface comprises forminga gate electrode having multi-layer sidewall spacers and a barrier layersuperjacent the gate electrode, wherein the barrier layer comprisessilicon oxynitride.
 3. The method of claim 2, wherein the gate electrodecomprises polysilicon and the barrier layer further comprises silicondioxide.
 4. The method of claim 1, wherein forming a recess comprisesplasma etching for approximately 15 seconds, in a parallel plate plasmareactor having a plate spacing of approximately 0.8 cm, a pressure ofapproximately 475 mT, an RF power of approximately 300 W, a Cl flow rateof 150 sccm, and a He flow rate of approximately 100 sccm.
 5. The methodof claim 4, wherein implanting ions comprises implanting nitrogen. 6.The method of claim 1, wherein implanting ions comprises implantingcarbon.
 7. A method of forming a source/drain terminal, comprising:masking a portion of the semiconductor surface; forming a recess in thesemiconductor surface adjacent to the masked portion, the recess havinga bottom portion and a side portion; forming a dielectric material overthe bottom portion of the recess such that the side portion of therecess is substantially exposed; and selectively forming a layercomprising silicon, beginning at the side portion of the recess andextending laterally away from the side portion.
 8. The method of claim7, wherein masking a portion of the semiconductor surface comprisesforming a gate electrode having sidewall spacers and a barrier layersuperjacent the gate electrode.
 9. The method of claim 8, wherein thegate electrode comprises polysilicon; the sidewall spacers comprise anoxide layer and a nitride layer; and the barrier layer comprises siliconoxynitride.
 10. The method of claim 7, wherein forming a recesscomprises plasma etching for approximately 15 seconds, in a parallelplate plasma reactor having a plate spacing of approximately 0.8 cm, apressure of approximately 475 mT, an RF power of approximately 300 W, aCl flow rate of 150 sccm, and a He flow rate of approximately 100 sccm.11. The method of claim 7, wherein the dielectric material comprisessilicon nitride.
 12. The method of claim 7, wherein the dielectricmaterial comprises silicon carbide.
 13. The method of claim 10, whereinforming a dielectric material over the bottom portion of the recesscomprises forming a morphologically nonconformal silicon nitride layer,the layer covering the bottom portion of the recess and the side portionof the recess, and wherein a portion of the layer covering the bottomportion of the recess is thicker and denser than a portion of the layercovering the side portion of the recess.
 14. The method of claim 13,further comprising removing the portion of the layer covering the sideportion of the recess.
 15. The method of claim 14, wherein removingcomprises etching in trimix.
 16. The method of claim 7, furthercomprising, prior to selectively forming a layer comprising silicon,cleaning the recess in an SF₆ plasma.
 17. A microelectronic structure,comprising: a substrate comprising a first crystalline material of afirst conductivity type the substrate having at least one recessedportion, the at least one recessed portion having a bottom surface and aside surface; an insulating layer disposed on the bottom portionsurface; and a second, substantially crystalline, material having asecond conductivity type disposed superjacent the insulating materialand adjacent a second portion of the substrate wherein the secondmaterial substantially fills the at least one recess.
 18. The structureof claim 17, wherein the first crystalline material is silicon, and theinsulating layer comprises a material selected from the group consistingof silicon nitride and silicon carbide.
 19. The structure of claim 18,wherein the second material comprises a material selected from the groupconsisting of silicon and silicon germanium.